This invention relates to architectures for a data cache, and to the circuit design of data cache components which enable the cache to operate at high speed.
By a data cache is herein meant an electronic circuit which stores multiple words of digital data and which also stores a respective compare address for each data word that is used in accessing a particular word of data. Each data word can be any type of digital information, such as a computer operand or a computer instruction for example.
One data cache architecture of the prior art consists essentially of a CAM (content addressable memory) in combination with a DATA RAM (random access memory). In operation, a compare address is sent to the CAM where it is compared with a plurality of N registers. Each such compare produces a respective match output signal MATCH.sub.i (i=1, 2, . . . N); and those MATCH.sub.i signals are then sent from the CAM to the DATA RAM where they select respective data words.
A drawback, however, of the above cache architecture is that the speed of the cache is limited by the speed of the CAM plus the speed of the RAM. This is because the CAM compare operation must be completed before the RAM read operation can begin. Further, an additional drawback is that as the number of registers in the CAM is increased, then a point is quickly reached where the CAM cannot be implemented on an integrated circuit chip. This is because each register produces a MATCH.sub.i signal which goes off the chip, and the total number of input/output pins on even the most advanced chips are limited to less than three-hundred.
A second data cache architecture, which is an improvement over the above cache, is comprised of an ADDRESS RAM and a comparator in combination with the DATA RAM. In operation, the compare address is partitioned into a high order portion A.sub.H and a low order portion A.sub.L ; and, address portion A.sub.L is used to read an address from the ADDRESS RAM and a data word the DATA RAM is parallel. Then, the address that is read from the ADDRESS RAM is compared to A.sub.H. If a match occurs, the data from the DATA RAM is valid; otherwise the data is invalid.
With this second architecture, the above described I/O pin limitation problem is overcome since only one comparison is made and so the multiple MATCH.sub.i signals are eliminated. However, with this second architecture, the speed of the cache becomes limited by the speed of the ADDRESS RAM plus the speed of the comparator. That is because the compare operation cannot occur until after the ADDRESS RAM is read.
Accordingly, a primary object of the invention is to provide a novel circuit, hereinafter called a random access compare array, which greatly increases the operating speed of a cache and which is not pin limited when implemented on an integrated circuit chip.